IIT Madras Invites Registrations for 'Future of India's Electronics and Computers' Symposium; Check Details

IIT Madras and IIT-M Pravartak Technologies Foundation are jointly hosting a one-day symposium on the future of electronics in India through the RISC-V pathway. The event will be held on August 6, 2023, at the IIT Madras Research Park in Taramani, Chennai. The registrations have been started, interested ones can enroll themselves.

All are invited to register for the symposium, which is free of charge and has a limited number of seats available. They can apply at the symposium's official website: pravartak.org.in/dirv_tech_confluence_registration.

RISC-V Symposium Brings Together Researchers, Industry Experts, and Students

The symposium intends to unite researchers, business experts, and students who are interested in Reduced Instruction Set Computer (RISC) V designs. The event's attendees will gain knowledge of the developing RISC-V ecosystem in India and examine the most recent advancements and trends in the field of processor design and innovation through open standard collaboration.

Rajeev Chandrasekhar, the Minister of State in the Ministries of Electronics and Information Technology, and Skill Development and Entrepreneurship, Government of India, as well as V Kamakoti, the director of IIT Madras, who played a key role in developing 'SHAKTI,' India's first indigenously-designed microprocessor based on RISC-V Instruction Set Architecture (ISA), will be present at the event.

Participants will be able to participate in an exciting hackathon finale, tour interactive booths demonstrating local RISC-V processors, and watch a special investor session. 

RISC-V: The Next Generation of Processor Architecture

The 'RISC' (Reduced Instruction Set Computer) architecture is distinct from the common 'CISC' (Complex Instruction Set Computer) architecture. The fifth generation is indicated by the letter "V" in RISC-V. The RISC-V project dates back to 2010, and its open standard collaboration and ISA have been crucial in enabling a new age of processor innovation. In order to set the stage for the next 50 years of innovative computing design, the RISC-V ISA is committed to giving a new degree of open, extensible software and hardware flexibility in computer architecture.

DIR-V Microprocessor Program to Take Center Stage at RISC-V Symposium in Chennai

One of the first members of the RISC-V Foundation, which was founded in 2015, is IIT Madras. The symposium takes place in conjunction with the ongoing DIR-V (Digital India RISC-V) microprocessor program. This initiative was started in 2022 by the Government of India with the audacious goal of enabling the creation of future-ready microprocessors in India for the global market and achieving industry-grade silicon and Design wins by December 2023.